For 7 nm technology nodes, a number of device options have been considered for forming a Fin-type field effect transistor (FinFET). For example, a single channel formed of a high-germanium (Ge) content silicon germanium (SiGe) n-type metal-oxide-semiconductor (nMOS) 101 and a high-Ge content SiGe p-type MOS (pMOS) 103 are formed on a bulk silicon (Bulk) layer 105, as depicted in FIG. 1A. For the purposes of this disclosure, high-Ge content is defined as at least 50%, low-Ge content is defined as less than 10%, and intermediate-Ge content is defined as anything between high and low Ge content. Adverting to FIG. 1B, a dual channel formed of a Si nMOS 121 and a high-Ge content SiGe pMOS 123 is formed over an intermediate-Ge content SiGe SRB (strain relaxed buffer) 125 and a Bulk layer 127. FIGS. 1A and 1B use bulk substrate and, therefore, have advantages in terms of substrate cost. However, forming the device of FIG. 1A is difficult because the high-Ge content SiGe is compressed on the Si substrate, which is not beneficial for an nFET. In addition, nFET gate and contact issues have not been solved. Similarly, forming the device of FIG. 1B is difficult because SRB technology has not sufficiently matured yet. Nevertheless, the use of the intermediate-Ge content SiGe SRB as depicted in FIG. 1B is advantageous because it can provide compressively stressed, high mobility pMOS channels with high-Ge contents and tensile stressed, high mobility nMOS devices with low (or no) Ge channels.
A known approach for forming a complimentary MOS (CMOS) is illustrated in FIGS. 2A and 2B. In particular, on the nFET side, a strained Si channel 201 and an intermediate-Ge content SRB 203, e.g., SiGe25, are formed over a Si substrate 205 and on the pFET side, a strained high-Ge content channel 207, e.g., SiGe50, and an intermediate-Ge content SRB 209, e.g., SiGe25, are formed over a Si substrate 211. However, there is often Ge diffusion at high temperature between different Ge concentrations, e.g., between the strained SiGe50 channel 207 and the SiGe25 SRB 209. In addition, the respective band-offset isolation between the strained Si channel 201 and the intermediate-Ge content SRB and the strained intermediate-Ge content channel and the intermediate-Ge content SRB may not be sufficient to prevent leakage. For example, a 25% concentration of Ge provides about 150 micro volt (mV) offset, which is insufficient from a device point of view, and increasing the Ge concentration delta fails due to lattice mismatch.
In addition, as CMOS devices continue to be decreased in size and scaled, current FinFET devices may not sufficiently reduce off-leakage current. A known approach to address this issue is the formation of nanowire devices. However, because most nanowire devices rely on a single material for both nFET and pFET similar to FIG. 1A, such devices are unable to provide the requisite channel strain.
A need therefore exists for methodology enabling formation of a FinFET device and a nanowire device each having dual-strained pMOS and nMOS from a common SRB, and the resulting devices.